ECO, or Engineering Change Order, is a vital step in the VLSI design flow, allowing engineers to implement fixes and optimizations at various stages of the design cycle. As modern chip designs grow increasingly complex, ECO plays a crucial role in ensuring design closure with minimal impact on cost, time, and resources.
Here is a detailed about the order of fixing in ECO specific to the physical design flow in VLSI:
1. Functional ECO
Purpose:
To correct logic-related issues and ensure the design operates as intended. Functional ECO is the foundation for all downstream fixes.
Key Tasks:
- Logic Changes: Resolve last-minute functional bugs by modifying the netlist (e.g., adding or removing gates, connecting missing signals).
- Scan Chain Modifications: Correct scan chain connectivity for testability.
- Reset and Clock Gating Fixes: Ensure proper reset behavior and reduce dynamic power with clock gating improvements.
Why First?
Functional changes impact the entire flow. For example, fixing incorrect logic or adding missing signal paths ensures that timing optimizations and physical corrections are working with a valid functional design.
2. DRV (Design Rule Violations) Fixes
Purpose:
DRVs ensure the design adheres to physical constraints such as maximum transition, maximum capacitance, and maximum fanout.
Common DRV Types:
- Max Transition Violations:
- Fix by upsizing drivers or inserting buffers to improve signal transition rates.
- Max Capacitance Violations:
- Fix by buffering long nets or cloning cells to reduce capacitance loads.
- Max Fanout Violations:
- Fix by cloning logic cells or restructuring the net to distribute fanout.
Why Now?
Fixing DRVs at this stage prevents cascading timing violations and ensures cleaner routing. DRVs impact how well timing and physical fixes can be applied later.
3. Crosstalk & Signal Integrity Fixes
Purpose:
Ensure signal integrity by addressing crosstalk, glitches, and other issues caused by routing proximity.
Key Techniques:
- Crosstalk Prevention: Add shielding or increase spacing between parallel nets.
- Glitch Avoidance: Insert buffers to reduce noise sensitivity.
- Driver Strengthening: Upsize drivers to combat noise or delay caused by crosstalk.
Why Now?
Crosstalk fixes might require routing adjustments that need to be applied after ensuring DRV fixes are stable.
4. Setup Timing Fixes
Purpose:
Address setup violations where data arrival is too late at the capture flop, causing incorrect operation.
Key Techniques:
- Cell Sizing: Upsize cells on critical paths to reduce logic delays.
- Buffer Insertion: Add buffers to optimize delays in long nets.
- Net Rerouting: Reduce wirelength to minimize propagation delay.
- Vt Swapping: Replace high-Vt cells with low-Vt cells to speed up signal transitions.
Why Before Hold Fixes?
Setup fixes tend to speed up paths, potentially introducing new hold violations. By handling setup timing first, we ensure stable data arrival before dealing with hold timing.
5. Hold Timing Fixes
Purpose:
Address hold violations where data arrives too early, disrupting the stability of the capture flop.
Key Techniques:
- Buffer Insertion: Introduce buffers to delay signal propagation.
- Wire Snaking: Increase wire length to add delay to critical nets.
- Cell Sizing: Downsize cells to slow down paths.
- Vt Swapping: Replace low-Vt cells with high-Vt cells to introduce delays.
Why After Setup Fixes?
Fixing hold violations after setup ensures that previously corrected critical paths are not impacted and maintains timing stability.
6. DRC/LVS Fixes
Purpose:
Design Rule Checks (DRC) ensure the layout complies with foundry-specific rules, while Layout Versus Schematic (LVS) ensures that the physical layout matches the netlist.
Key Issues Addressed:
- Short/Open Violations: Fix connectivity issues in routing.
- Antenna Violations: Add diodes or adjust routing to resolve excess charge accumulation.
- Spacing and Width Violations: Adjust placement or routing to meet minimum/maximum spacing rules.
- Metal Density Violations: Add dummy fill to maintain metal density requirements for manufacturability.
Why Now?
Timing and hold fixes might introduce physical violations, so DRC/LVS fixes come afterward to clean up any issues before finalizing the design.
7. Power & IR Drop Fixes
Purpose:
Ensure that the design meets power budgets and avoids power integrity issues such as IR drop and electromigration (EM).
Key Techniques:
- IR Drop Fixes: Add power straps or vias to ensure sufficient power delivery.
- EM Fixes: Widen power and clock nets to handle current density limits.
- Clock Power Optimization: Minimize power consumption in the clock tree through gating and optimization.
Why Now?
Power and IR drop fixes often involve routing changes that need a stable layout with no major DRV or timing violations.
8. Final Signoff Checks
Purpose:
Perform final validation to ensure the design meets all functional, timing, and physical requirements before tape-out.
Key Checks:
- Static Timing Analysis (STA): Confirm setup/hold timing closure across all corners. It is done using PrimeTime [Synopsys] or Tempus [Cadence].
- Design Rule Checks (DRC): Ensure no remaining physical design rule violations. It is done using Calibre [Mentor Graphics/Siemens] or IC Validator [Synopsys].
- Layout Versus Schematic (LVS): Verify that the layout matches the schematic. It is done using Calibre [Mentor Graphics/Siemens] or IC Validator [Synopsys].
- Logical Equivalence Check (LEC): Ensure functional equivalence between the final netlist and the RTL design. It is done using Formality [Synopsys] or Conformal LEC [Cadence].
- Power Analysis: Validate IR drop, electromigration, and overall power consumption. It is done using RedHawk [Ansys] or Voltus [Cadence].
Why Last?
Final checks ensure that all previous fixes have been applied correctly and no new issues are introduced before tape-out.
Why is ECO Essential?
ECO enables targeted modifications at the late stages of design without disrupting the entire workflow. It provides designers with flexibility to address unforeseen issues, optimize the design, and meet critical constraints efficiently.
By following the structured steps of functional fixes, timing closure, power optimization, and verification, design teams can ensure a reliable, high-quality chip ready for tape-out.
Conclusion
The optimized order of fixes during the ECO phase is as follows:
- Functional Fixes (Logic, scan chains, clock gating, resets).
- DRV Fixes (Max transition, capacitance, and fanout violations).
- Crosstalk & SI Fixes (Addressing signal integrity issues).
- Setup Timing Fixes (Speeding up critical paths).
- Hold Timing Fixes (Slowing down early paths).
- DRC/LVS Fixes (Correcting physical violations).
- Power & IR Drop Fixes (Improving power delivery and integrity).
- Final Signoff Checks (STA, DRC, LVS, LEC, and power analysis).
By following this structured approach, designers ensure a clean and efficient design closure during the ECO phase, achieving timing, power, and physical integrity for tape-out.
